Replacement control gate methods and apparatuses

ABSTRACT

Disclosed are memory structures and methods for forming such structures. An example method forms a vertical string of memory cells by forming an opening in interleaved tiers of dielectric tier material and nitride tier material, forming a charge storage material over sidewalls of the opening and recesses in the opening to form respective charge storage structures within the recesses. Subsequently, and separate from the formation of the floating gate structures, at least a portion of the remaining nitride tier material is removed to produce control gate recesses, each adjacent a respective charge storage structure. A control gate is formed in each control gate recess, and the control gate is separated from the charge storage structure by a dielectric structure. In some examples, these dielectric structures are also formed separately from the charge storage structures.

PRIORITY APPLICATION

This application is a divisional of U.S. application Ser. No.15/555,046, filed Aug. 31, 2017, which is a U.S. National StageApplication under 35 U.S.C. 371 from International Application No.PCT/US2016/022672, filed Mar. 16, 2016, which claims the benefit ofpriority to U.S. Provisional Application Ser. No. 62/134,338, filed Mar.17, 2015, all of which are incorporated herein by reference in theirentirety.

BACKGROUND

Memory devices can be provided as internal, semiconductor, integratedcircuits in computers or other electronic devices. There are manydifferent types of memory including random-access memory (RAM), readonly memory (ROM), dynamic random access memory (DRAM), synchronousdynamic random access memory (SDRAM), and non-volatile (e.g., flash)memory.

Flash memory devices typically use a one-transistor memory cell that mayallow for high memory densities, high reliability, and low powerconsumption. Changes in threshold voltage of the memory cells, throughprogramming of a charge storage structure such as floating gates,trapping layers or other physical phenomena, may determine the datastate of each cell.

The memory cells may be arranged in strings of memory cells where eachstring may be coupled between a drain and a common source. Relativelyrecently, memory cell strings are being fabricated vertically in orderto fit more memory cells on a semiconductor memory device and therebyincrease the memory density of memory devices.

Many conventional processes of fabricating vertical strings of memorycells may result in various problems, including residual nitrideremaining in undesirable locations when “flanking” (e.g., U-shaped)nitride results from the fabrication process. It would be desirable toimprove the vertical memory cell string fabrication process to yield animproved cell architecture

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematic diagram of an apparatus comprising astring of memory cells, according to various embodiments.

FIGS. 2-34 each depict a representative portion of a memory array at arespective processing stage in an example semiconductor fabricationprocess for constructing vertical strings of memory cells havingreplacement control gates; with FIGS. 2-21 and 23-34 illustrated from anoblique perspective, and FIG. 21, depicted from an upper, plan,perspective.

FIG. 35 illustrates a block diagram of an embodiment of a memory device,according to various embodiments.

DETAILED DESCRIPTION

The present description addresses a representative semiconductorfabrication process for forming a memory device including verticalstrings of memory cells; and particularly wherein the memory cells have“replacement” control gates. For purposes of the present description,the term “replacement control gate” refers to a control gate of a chargestorage access device that is fabricated after the charge storagestructure has been fabricated. For purposes of the example structureused herein to describe an example manufacturing process flow, thecharge storage structure will be a floating gate transistor, and theaccess gate of the transistor will be formed after formation of thefloating gate. Some process flows in accordance with the teachingsherein may avoid the creation of a flank (U-shaped) nitride structurethat essentially surrounds the charge storage structure, as is producedwith some conventional process flows.

In the following description various terms are used to describe therelative placement or orientation of structures. The term “horizontal”as used in this description is refers to a plane parallel to theconventional plane or surface of a substrate, such as that underlying awafer or die, regardless of the actual orientation of the substrate atany point in time. The term “vertical” refers to a direction generallyperpendicular to the horizontal as defined above. Prepositions, such as“on,” “over,” and “under” are defined with respect to the conventionalplane or surface being on the top or exposed surface of the substrate,regardless of the orientation of the substrate; and while “on” isintended to suggest a direct contact of one structure relative toanother structure which it lies “on” (in the absence of an expressindication to the contrary); the terms “over” and “under” are expresslyintended to identify a relative placement of structures (or layers,features, etc.), which expressly includes—but is not limited to—directcontact between the identified structures unless specifically identifiedas such. Similarly, the terms “over” and “under” are not limited tohorizontal orientations, as a structure may be “over” a referencedstructure if it is, at some point in time, an outermost portion of theconstruction under discussion, even if such structure extends verticallyrelative to the referenced structure, rather than in a horizontalorientation. Similarly, identification of two structures being“adjacent” is meant to describe a general proximity to one another(within the context of the dimensions of the structures describedherein), and does not suggest either the presence or absence of anyintervening materials or structures (in other words two nearbystructures are adjacent within the meaning of this description whetherthey are in contact with one another, or separated by an interveningstructure).

FIG. 1 depicts a schematic representation of an apparatus comprising astring 100 of memory cells, according to various embodiments. Forpurposes of illustration only, the string 100 is shown having 16 memorycells 112. Alternate embodiments can include more or less than 16 memorycells 112. In this example, the string 100 includes a source select gatetransistor 120 (e.g., SGS, n-channel) where the source select gatetransistor 120 is coupled between one of the memory cells 112 at one endof the string 100 and a common source 126. The common source 126 maycomprise, for example, a slot of commonly doped semiconductor materialand/or other conductive material. The common source 126 may be common toone or more additional strings of memory cells that together form amemory array or device, or a portion thereof.

At an opposite end of the string 100, a drain select gate transistor 130(e.g., SGD, n-channel) includes a transistor 130 coupled between one ofthe memory cells 112 (in this example, located at the opposite end ofstring 100), and a data line (e.g., bit line) 134. In some examples, thedata line 134 may also be common to one or more additional strings ofmemory cells in the memory array or device.

In this example, each of the memory cells 112 includes a charge storagestructure. In the examples discussed herein the charge storage structurewill be described as a floating gate transistor; though other chargestorage mechanisms may be used instead, such as, for example, a chargetrap transistor, or other forms of charge storage mechanisms. The memorycells 112 may be configured to be either a single level charge storagedevice (SLC) or multilevel charge storage device (MLC), with double ortriple (or more) levels of charge storage capability.

In the depicted example, the memory cells 112, the source select gatetransistor 120, and the drain select gate transistor 130 will becontrolled by signals on their respective control gates. In anembodiment, the control gates of memory cells 112 in a row of memorycells can form part of an access line (e.g., word line) WL0-WL15. Thesignals to control the memory cells 112 may be provided on theirrespective access line.

The source select gate transistor 120 may receive a control signal thatcontrols the source select gate transistor 120 to substantially controlconduction between the string 100 and the common source 126. The drainselect gate transistor 130 may receive a control signal that controlsthe drain select gate transistor 130, so that the drain select gatetransistor 130 can be used to select or deselect the string 100.

The string 100 can be one of multiple strings of memory cells 112 in ablock of memory cells in a memory device, such as a NAND-architectureflash memory device. Each string 100 of memory cells 112 may be formedvertically such that they extend outward from a substrate as opposed tobeing disposed in a planar manner along the surface of the substrate.Other embodiments may use other types of memory architecture such as,for example, NOR flash memory architecture.

FIGS. 2-34 depict a representative portion of a memory array at arespective processing stage in an example semiconductor fabricationprocess for constructing vertical strings of memory cells havingreplacement control gates. The figures depict the fabrication ofmultiple vertical strings of memory cells. The described fabricationprocess may be used to fabricate any number of vertical strings ofmemory cells in a memory array or device.

In the embodiments of FIGS. 2-34, the drain select gate and sourceselect gate transistors are shown being fabricated with the same flowprocess that forms the memory cells of the vertical string of memorycells. However, other embodiments may fabricate the drain select gatetransistor and/or the source select gate transistor at different timesfrom the flow shown in FIGS. 2-34. For example, the source select gatetransistor may be fabricated prior to the fabrication flow shown inFIGS. 2-34. Similarly, the drain select gate transistor may befabricated at the same time as the rest of the vertical string of memorycells or it may be fabricated after the vertical string of memory cells.

Referring to FIG. 2, a stack 200 of interleaved tiers of semiconductormaterials 201-209 is formed (e.g., deposited) on the source select gatematerial 210. The semiconductor materials may include tiers of adielectric material (e.g., for example an oxide material) (termed hereinas “dielectric material” tiers) 201, 203, 205, 207, 209 which arevertically spaced from one another in the stack, and separated from oneanother, at least in part by tiers of a barrier material, such as anitride-containing material 202, 204, 206, 208 (e.g., termed hereineither “barrier material” tiers or “nitride material” tiers). Thisrelationship of the tiers is referred to herein as “interleaved” tiers.For purposes of simplifying the present example, a limited number ofdielectric material tiers and nitride material tiers are depicted in thereferenced Figures. In most cases, an actual device would includeadditional pairs of both types of tiers; and would include at least adielectric material tier and a nitride material tier for each memorycell to be formed in the vertical string (i.e., the interleaved tierstack 200 to construct the memory cell portion of a vertical string asdiscussed in reference to FIG. 1, structure would include at least 16dielectric material tiers, with at least 16 barrier material tiersinterleaved therewith).

The dielectric material tiers 201, 203, 205, 207, 209 include, in thisexample, silicon dioxide (SiO₂); or may include other low trapping oxidematerials, such as those having a lower dielectric constant than that ofSiO₂ (e.g., 3.9). Also, in this example, the nitride material tiers 202,204, 206, 208 include, for example, silicon nitride (Si₃N₄), titaniumnitride (TiN), tantalum nitride (TaN), other nitride materials; or mayinclude other materials that may be relatively easily removable andselectively removable relative to the oxide layers 201, 203, 204, 207.While in some examples, and as depicted in FIG. 2, stack 200 may includea vertical section in which dielectric material tiers and nitridematerial tiers are formed directly one upon the other; such structure isnot required and other material layers, such as other electricallyinsulating layers or similar structures may be vertically interspersedbetween the described interleaved dielectric material tiers and nitridematerial tiers.

In the depicted example, the dielectric material tiers 201, 203, 205,207, 209 are formed having a greater thickness than the nitride materialtiers 202, 204, 206, 208. For example, the dielectric material tiers201, 203, 205, 207, 209 may be formed to a thickness of a range of about35-40 nanometers (nm) while the nitride material tiers 202, 204, 206,208 may be formed to a thickness of a range of about 15-20 nm. Thesethicknesses are for purposes of illustration only as the disclosedembodiments are not limited to any particular thicknesses.

The dielectric material tiers 201, 203, 205, 207, 209 can also be orinclude, for example, a relatively low leakage, high-K (e.g., greaterthan 3.9) dielectric material. For example, these tiers 201, 203, 205,207, 209 may include hafnium dioxide (HfO₂) or zirconium dioxide (ZrO₂).

If the source select gate transistor is being fabricated with the flowof FIGS. 2-34, the interleaved tier stack 200 may be formed (e.g.,deposited) above the SGS material 210 (e.g., polysilicon). The SGSmaterial 210 may be formed over an isolating dielectric material 211(e.g., oxide) that may serve to isolate the SGS material 210 from thecommon source node material 212, as well as other from layers of thesemiconductor structures or the substrate 250 (e.g., bulk silicon).

FIG. 3 depicts one option for a subsequent stage of thethree-dimensional view of semiconductor fabrication flow providingadditional structures relative to those described and discussed inreference to FIG. 2. In this example, the drain select gate transistorfor the vertical array of memory cells will be fabricated with the restof the vertical string of memory cells, and thus the SGD material 302 isformed (e.g., deposited) over the interleaved tier stack 200. In anembodiment, the SGD material 302 is a polysilicon.

A cap dielectric material 301 (e.g., oxide) may be formed over the SGDmaterial 302. A patterned hard mask 300 (pattern not depicted) may beformed (e.g., deposited) over the SGD material 302. If the drain selectgate transistor is fabricated after the rest of the vertical string ofmemory cells, the patterned hard mask 300 may be formed over theinterleaved tier stack 200. The patterned hard mask 300 may be used asan etch resistant material during a subsequent etching process. Thepatterned hard mask 300 may be, for example, an amorphous carbon,undoped polysilicon hard mask or some other etch resistant material.While the drain select gate transistors may be formed separately fromthe further processing of the tier stack 200; for purposes of describingthe example processing flow surrounding stack 200, subsequent FIGS. 4-34and accompanying discussion will describe a process flow which includesforming of the drain select gate transistors with processing of thestack, as indicated by this FIG. 3.

FIG. 4 depicts the structure of FIG. 3 after the patterned mask layer300 of that figure has been utilized to form openings 400 (e.g., byetching through the cap oxide 301, the SGD material 302, the interleavedtier stack 200, and the SGS material 210). The openings 400 will, insubsequent processes, contain the respective pillars for each of thevertical strings of memory cells.

The openings 400 may be etched using reactive ion etch (RIE) techniques,which will typically be preferred as opposed to wet chemical etches. Theetch process may be more or less non-isotropic (directional) so that, inan embodiment, the sides of the openings are substantially close toforming an angle of 90° with respect to the substrate surface. Inanother embodiment, the sides may have some slope and the slope may varyalong the depth of the pillar opening. In many example, the openings mayhave a depth in a range of about 1 μm to about 5 μm, as measured fromthe surface or layer 301, depending on the number of cells in the stringbeing integrated. Of course, greater depths are possible where thestructure is to include a greater number of memory cells in the verticalstring.

FIG. 5 depicts the structure of FIG. 4 after forming of lateral recesses500 in the nitride material tiers 202, 204, 206, 208 of the interleavedtier stack 200. The recesses 500 each surround a respective opening 400.Each recess 500 may be formed to be approximately equal to a thicknessof a charge storage material (in this example, a floating gatestructure) that will subsequently be formed in the recesses 500. Forexample, the recesses may be formed to a range of about 10-20 nm.

The recesses 500 may be formed by a selective, isotropic etch process.For example, a vapor etch may be used to etch the nitride material tiers202, 204, 206, 208 laterally while not etching the dielectric materialtiers 201, 203, 205, 207, 209. Such an etch process may include a wet orchemical etch process.

FIG. 6 depicts the structure of FIG. 5 after forming of a linerdielectric 602 (e.g., oxide) over the nitride material tiers 202, 204,206, 208 in the recesses 500. The liner dielectric 602 may be relativelythin (e.g., approximately 15 Angstroms (Å)), functioning to isolate thenitride material tiers 202, 204, 206, 208 from a subsequently formedfloating gate material (e.g., polysilicon). The liner dielectric 602 maybe formed by an oxidation process (e.g., grown) or a deposition process.

If the SGD and SGS transistors are formed in the same flow asillustrated in FIGS. 2-34, a liner dielectric 601, 603 may be formed, inthe same step as the liner dielectric 602, over the respective SGDmaterial 302 and SGS material 210, in order to separate each of the SGSand SGD materials 210, 302, respectively (e.g., in most cases each willinclude polysilicon) from a subsequent polysilicon forming a pillar inthe opening that may have a different doping level and doping type fromthe SGD and SGS polysilicon 210, 302.

FIG. 7 depicts the structure of FIG. 6 after forming of a floating gatematerial 700 (e.g., polysilicon), usually by deposition over thesidewalls of each of the openings 400 and in contact with the sidewallsthen defining each opening 400 (e.g., adjacent dielectric materialtiers), and within the nitride tier recesses 500. The material 700 inthe recesses 500 will form the floating gate for each of the memorycells. The floating gate material 700, for example, may be deposited toa depth of approximately greater than the nitride thickness divided bytwo. For example, the floating gate material may be deposited to a depthof greater than approximately 10 nm on the sidewalls of the openings 400and recesses 500 such that the floating gate material 700 substantiallyfills each of the nitride tier recesses 500 by the recess sidewallmaterial joining in the middle of each of the recesses. As discussedpreviously, the liner dielectric 601-603 separates the floating gatematerial 700 from the SGD and SGS material as well as the individualnitride material tiers. If the floating gate material 700 is apolysilicon, the polysilicon may be doped or undoped. In anotherembodiment, the floating gate material may include one or more of ametal, a metal composite, and metal nano dots embedded in a dielectric.

FIG. 8 depicts the structure of FIG. 7 after forming of a partialsacrificial oxide 800 over the floating gate material 700. Partialsacrificial oxide may be formed over the floating gate material 700,preferably by consuming only a particular portion (e.g., less than all)of the underlying floating gate material 700 over the sidewalls. Athickness of the sacrificial oxide 800 is determined such that, when asubsequent etching process is performed to remove the sacrificial oxide800, only a particular portion (e.g., approximately 7 nm) of theunderlying floating gate material 700 is oxidized to become asacrificial oxide 800 to be removed. The thickness of the sacrificialoxide 800 determines the amount of underlying floating gate material 700that is removed. For example, making the sacrificial oxide 800 thicker,results in less floating gate material 700 being removed from thesidewalls of the openings during the etching process (e.g., therebyleaving a thicker layer of polysilicon over the sidewalls). Since theremaining floating gate material 700 eventually becomes the tunneldielectric, as seen in a subsequent flow process, this process alsodetermines the thickness of the tunnel dielectric.

FIG. 9 depicts the structure of FIG. 8 after a partial floating gatepoly cut (e.g., etching process) to remove the sacrificial oxide 800. Inaddition to the floating gate material 700 remaining in the recesses ofthe openings, a reduced thickness of floating gate material 700 nowremains on the sidewalls of the openings 400 (e.g., approximately 30 Å).This material 700 may preserve the pillar cross-sectional diameterthrough future process steps.

FIG. 10 depicts the structure of FIG. 9 after forming of a tunneldielectric 1000. Tunnel dielectric material 1000 is formed (e.g.,grown), for example, by oxidation of the remaining floating gatematerial 700 on the sidewalls of the openings. The floating gatematerial (e.g., polysilicon) on the sidewalls of the openings isconsumed by the tunnel oxide growth. This may result in the inner pillarcross-section diameter being reduced by a particular thickness (e.g.,about 10-14 nm total). This same tunnel oxide 1000 may be grown on theSGS material 210 and SGD gate to concurrently form the gate dielectricfor these respective devices.

The oxidation may have the benefit of resulting in a pure oxide in boththe cells and the SGD/SGS gate dielectrics. The oxidation may alsoreduce tier expansion since the oxidation has minimum encroachment totier nitride since it oxidizes the sidewall poly initially and consumesthe sidewall floating gate material such that only the floating gatematerial in the nitride material tiers remains. As an alternative to theabove flow, however, the sacrificial oxide discussed in reference toFIG. 7 might not be limited to only a portion of the thickness of thepolysilicon on the sidewalls, but might be formed to oxidize allpolysilicon over the sidewalls, leaving only the portion in the recessesunoxidized to form the floating gate structures therein. In thisalternative process, removal of the sacrificial oxide will remove all,or at least most, of the polysilicon over the sidewalls that could havebeen used for forming a tunnel oxide. As a result, in this alternativeprocess, a tunnel oxide would be deposited over the sidewalls andfloating gate structures (rather than being grown from remainingpolysilicon, as discussed above)

FIG. 11 depicts the structure of FIG. 10 after forming of a sacrificialpolysilicon liner material 1100. Sacrificial polysilicon liner material1100 is formed (e.g., deposited) over the tunnel dielectric material1000 formed (e.g., grown) in the embodiment of FIG. 10 The linermaterial 1100 is formed (e.g., deposited) over the opening sidewalls andfloating gates of the cells

FIG. 12 depicts the structure of FIG. 11 after a punch operation (e.g.,very directional dry etch) is performed to remove the stack top portionof the polysilicon liner material 1100 of FIG. 11 as well as polysiliconliner material 1100 at the bottom 1220 of each opening but not removethe material on the sidewall of the pillar opening (e.g., the tunneloxide is protected from this punch). The punch operation exposes anupper portion 1200 of the polysilicon liner material 1100 from theopenings that has been surrounded and protected by the oxide 1000. Thepunch also exposes the oxide layer 211 between the bottom 1220 of theopenings and the common source node material 212. The punch operationmay be a directional (non-isotropic) etch process.

FIG. 13 depicts the structure of FIG. 12 after the protective oxide 1000is removed (e.g., wet oxide etch) to expose the source node material 212at the bottom 1300 of each opening. Thus, after the subsequent polyliner removal (PLR) process, the contacting area to the source isenlarged.

FIG. 14 depicts the structure of FIG. 13 after the polysilicon linermaterial 1100 is removed by a PLR process (e.g., an isotropic etch veryselective to oxide) to expose the tunnel dielectric material 1000 whilekeeping the tunnel dielectric material 1000 intact.

FIG. 15 depicts the structure of FIG. 13 after the formation of a pillarmaterial 1500 in the openings. A pillar material (e.g., polysilicon)1500 is formed (e.g., deposited) on the then sidewalls of the openingsas well as over the oxide cap 301. The pillar material may be formed toa thickness (e.g., approximately 10 nm) and is generally conformal alongthe sidewalls and bottom of the pillar openings (e.g., contacting thecommon source node) to act as a channel for the memory cells. Anoptional inner sidewall treatment (e.g., thermal oxidation) may beperformed in order to improve channel conduction properties. Thisthickness for the pillar material will, in many examples, leave acentral void in the pillar, which will be filled.

FIG. 16 depicts the structure of FIG. 15 after the filling of the voidsin the pillar material 1500. In this example process flow, dielectricmaterial (e.g., oxide) 1600 is formed in the openings of the pillarmaterial 1500. A spin-on process may be used to form the oxide 1600 andfill the voids. Pre and/or post thermal treatment of this spin-ondielectric may be performed for device performance improvement.

FIG. 17 depicts the structure of FIG. 16 after removal of the pillarmaterial 1500 and dielectric material 1600 on top of the stack. This maybe accomplished by a spin oxide chemical mechanical polishing (CMP)operation that stops on the pillar material 1500 and a pillar poly CMPthat stops on the cap oxide 301. Thus, the tops 1700 of the filledpillar openings are exposed and isolated from one another.

FIG. 18 depicts the structure of FIG. 17 after the forming of a recess1800 in the tops of the pillar oxide 1600. This may be accomplished bycontrolled oxide wet etch process.

FIG. 19 depicts the structure of FIG. 18 after the forming of a plugmaterial in the recesses 1800. A plug material 1900 is formed (e.g.,deposited) over the top of the stack and into the recesses 1800 abovethe pillars. In an embodiment, the plug material 1900 is a dopedpolysilicon.

FIG. 20 depicts the structure of FIG. 19 after the plug material 1900 ontop of the stack is removed to leave only the plug 2000 (e.g.,polysilicon) isolated (from other pillars) over each pillar. The removalof the plug material 1900 may be accomplished by a polysilicon CMP. Theplug 2000 acts as the drain to tie to the channel, which may be turnedon or off by the SGD/SGS and other control gates and is eventuallycoupled to data lines (e.g., bit lines) of the memory.

FIG. 21 depicts the structure of FIG. 20 after a protective material2100 (e.g., oxide) is formed (e.g., deposited) over the top of the stackas a protective oxide. The protective material 2100 provides protectionof the fabricated charge storage structure from further processing as areplacement control gate is fabricated.

FIG. 22 schematically depicts a portion of the structure after theoperation discussed relative to FIG. 20 (and without the protectivelayer of FIG. 21), depicted here from a top view after the formation oftrenches 2200 and 2201. Thus, FIG. 22 shows the plugs 2000 of eachpillar under the protective material 2100 as well as trenches 2200,2201. As described subsequently with reference to FIGS. 23 and 24, thetrenches 2200, 2201 may be used to separate memory blocks. The trenches2200, 2201 cut through and separate access lines (e.g., word lines), SGDtransistor control lines, and (optional) SGS transistor control lines inorder to provide self-contained address units for each memory block. Thetrenches 2200, 2201 are used in the example process flow to form wordlines from outside the pillars as disclosed subsequently. The SGStransistor control lines are not described herein as these lines werepredefined as the gaps in layer 210 of FIG. 2 prior to forming thestack.

In an embodiment, the pillars may be located about 150 nm frompillar-center to pillar-center and the trenches 2200, 2201 spaced apartby about 600 nm or more. These distances are for purposes ofillustration only as other embodiments may use different distances.

The following described fabrication flow diagrams of FIGS. 23-34 providedetails for fabrication of a replacement control gate for theabove-described charge storage structure. As noted earlier herein, a“replacement control gate” as used herein refers to a control gate thatis fabricated after the charge storage structure has been fabricated, asdescribed previously with reference to FIGS. 2-21.

FIG. 23 depicts the structure of FIG. 21 after forming of a hard maskmaterial layer. Hard mask material 2300 is formed (e.g., deposited) overthe protective material 2100 of the charge storage stack structure 2310.The hard mask material 2300 may be, for example, a nitride hard mask orsome other etch resistant material. A photolithography process may beused to produce a trench pattern 2301 over the hard mask material 2300.

FIG. 24 depicts the structure of FIG. 23 after the hard mask material2300 is patterned by an etch process to form trenches 2400, 2401 in thehard mask material 2300.

FIG. 25 depicts the structure of FIG. 24 after forming of trenches 2200and 2201. Using the patterned hard mask material 2300, a deep trenchetch process may be used to form the trenches 2200, 2201 through thecharge storage structure 2310 down to an etch stop material 2510, 2511(e.g., oxide). The etch stop material 2510, 2511 may have been formedover the substrate during formation of the interleaved tiers, oralternatively the etch stop material 2510, 2511 may be formed during thepresent flow process of forming the trenches 2200, 2201. As identifiedpreviously, the trenches 2200, 2201 separate groups of vertical stringsof memory cells (e.g., memory blocks). The hard mask material 2300 isremoved during this process leaving the protective material 2100 on topof the charge storage structure 2310. As a result of this process, itcan be seen that the exposed surfaces of the interleaved dielectricmaterial tiers and nitride material tiers form a portion of thesidewalls defining the trenches.

The trenches 2200, 2201 are shown dividing the charge storage structure2310 up into separate memory blocks 2521, 2522. Thus, each of thesubsequently fabricated replacement control gates may be associated witha different respective memory block 2521, 2522.

FIG. 26 depicts the structure of FIG. 25 after etching of the nitridematerial tiers 202, 204, 206, 208. The nitride material tiers 202, 204,206, 208 (as seen in FIG. 2) are removed up to the dielectric liner 602(e.g., oxide). For example, an isotropic etch process may be used toselectively remove the nitride material tiers 202, 204, 206, 208 withoutremoving the oxide liners 602 or dielectric material tiers 201, 203,205, 207, 209. This forms control gate recesses in the tiers, adjacentto the floating gates, in what used to be nitride material tiers.

FIG. 27 depicts the structure of FIG. 26 after etching of dielectricmaterial tiers 201, 203, 205, 207, 209. The control gate recesses 2700resulting from the nitride tier removal are enlarged by reducing thethickness of the dielectric material tiers 201, 203, 205, 207, 209. Thethickness reduction may be accomplished by a controlled isotropic oxideetch process, such as self-timing vapor oxide etch. These control gaterecesses will house the control gates as well as the associateddielectric structures that will lie between each control gate and anadjacent floating gate. In many examples processes, the dielectricstructure will extend around the top and bottom of the control gate. Asa result of the increased vertical dimension of the control gaterecesses achieved by reducing the thickness of the vertically adjacentdielectric material tiers, the control gates and associated dielectricstructures can have a vertical dimension that is greater than thevertical dimension of the adjacent floating gate. As the control gatesand associated dielectric structures will fill the vertical extent ofthe associated control gate recesses, the vertical dimension of thecontrol gates and associated dielectric structures in each control gaterecess will be greater than the vertical dimension of the nitridematerial layers in which they are located.

FIG. 28 depicts the structure of FIG. 27 after a dielectric material2810-2813 (e.g., oxide) is formed (e.g., deposited, grown) on thebackside of the floating gate material in the control gate recesses. Adielectric material 2800, 2801 (e.g., oxide) is also formed (e.g.,deposited, grown) on the SGS and SGD materials. In an embodiment, anoxidation process of the polysilicon may be performed to grow the oxide2800, 2801, 2810-2813.

FIG. 29 depicts the structure of FIG. 28 after a nitride material 2900is formed (e.g., deposited) over the sidewalls of the trenches as wellas the sidewalls of the control gate recesses 2700.

FIG. 30 depicts the structure of FIG. 29 after formation of amulti-component dielectric structure 3000 is formed (e.g., grown,deposited) over the nitride material 2900 of the trench sidewalls andsidewalls of the control gate recesses. The multi-component dielectricstructure will preferably be an oxide-nitride-oxide (ONO) dielectricstructure; and the dielectric structure will be formed adjacent to thefloating gates in each tier, separating the subsequent control gatematerial from the floating gate (and in many cases extending above andbelow the control gate). The ONO dielectric is formed separately fromthe floating gate. The ONO dielectric preferably includes a relativelylow leakage, high-K dielectric material (e.g., greater than 3.9). Forexample, the ONO dielectric may include ZrO₂, HfO₂, Al₂O₃, or mixturesof these oxides.

FIG. 31 depicts the structure of FIG. 29 after a metal liner material3100 (e.g., titanium nitride (TiN), tungsten nitride (WN), tantalumnitride (TaN)) is formed (e.g., deposited) over the dielectric material3000 of the trench sidewalls and the tier control gate recess sidewalls.In an embodiment, the metal liner material 3100 may be deposited by anatomic layer deposition (ALD) process to a depth of, for example,approximately 2-3 nm.

FIG. 32 depicts the structure of FIG. 29 after a control gate material3200 (e.g., metal or polysilicon) is formed (e.g., deposited) over themetal material 3100 of the trench sidewalls and the tier openingsidewalls. In an embodiment, the control gate material 3200 may bedeposited by an ALD process to a depth of a range of approximately 5-10nm. If the control gate material is a doped polysilicon, the previousprocess of the metal liner material 3100 may not be performed. If thecontrol gate material is a metal, the metal may be, for example,tungsten (W), titanium (Ti), tantalum (Ta), or other highly conductivemetals. The metal liner material, when present, forms a portion of thecontrol gate.

FIG. 33 depicts the structure of FIG. 29 after the metal material 3100(e.g., TiN) and the control gate material 3200 (e.g., W) is removed (Wis removed prior to TiN) from the sidewalls of the trenches to leave themetal material 3100 and the control gate material 3200 only in the tieropenings to form the control gates 3300 (e.g., access lines, word lines)for the previously formed floating gates memory structure. An isotropicRIE etch process may be used to remove these materials 3100, 3200 fromthe trench sidewalls.

FIG. 34 depicts the structure of FIG. 29 after the previous dielectricmaterial 3000 and nitride material 2900 are removed from the sidewallsof the trenches 2200 to provide individual access line separation. Thus,FIG. 34 shows that an access line 3400 extends into the page along they-axis. Each of the individual access lines 3400 may then be coupled toaddressing circuitry (not shown) in order to provide the voltages usedduring memory cell operation. The trenches are filled and planarized forsubsequent back end metallization/interconnect processes. A dielectricmaterial (e.g., oxide) may be used to fill the trenches.

FIG. 35 illustrates a block diagram of an embodiment of a system, inaccordance with various embodiments. The system can include a controller3500 (e.g., control circuitry, microprocessor) coupled to a memory array3501 over address, control, and data buses. In one embodiment, thecontroller 3500 and memory array 3501 may be part of the same memorydevice. In another embodiment, the memory array 3501 is part of a memorydevice and the controller 3500 is a separate integrated circuit. Thememory array 3501 may include vertical strings of memory cells withreplacement control gates as described previously.

The above-described semiconductor fabrication flow for vertical stringsof memory cells having replacement control gates may provide benefitsover conventional vertical memory cell strings by decoupling thefloating gate formation from the control gate formation, therebyreducing or eliminating residual nitride from sidewalls of the pillarsto reduce undesirable electron trapping, eliminating flank nitridearound the floating gates to reduce undesirable electron trapping andimprove endurance, and/or reduce minimum cross-sectional diameter tobenefit the program/erase V_(t) window and efficiency in programmingslope. Additional benefits may also be realized such as no ONO oroxynitride as a gate dielectric material on the SGS and SGD transistors,thus reducing V_(t) degradation from cycling; a lower access lineresistance if a metal control gate is used; and the potential forvertical scaling of the tiers with a shorter floating gate height.Additionally, with the described process flow, the vertical dimension ofthe control gate is not tied to that of the floating gate, thus furtherfacilitating vertical scaling of the tiers. Tighter process control and,hence, cell device variability reduction may be achieved with the flowdescribed here since the floating gate formation depends on only oneprocess variable (e.g., tier nitride recess), as opposed to four processvariables as used in the current state of the art practice.

An apparatus may be defined as circuitry, an integrated circuit die, adevice, or a system.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Accordingly, manymodifications and variations may be made in the structures andtechniques described and illustrated herein without departing from thescope of the inventive subject matter. This application is intended tocover any adaptations or variations; and the scope of the inventivesubject matter is to be determined by the scope of the following claimsand all additional claims supported by the present disclosure, and allequivalents of such claims.

What is claimed is:
 1. An apparatus comprising: a memory arrayincluding, multiple tiers of dielectric material vertically offset fromone another; multiple tiers of barrier material interleaved with themultiple tiers of dielectric material and also vertically offset fromone another, each barrier material tier including charge storagestructures, and further including control gates, each control gateadjacent a respective charge storage structure; wherein each controlgate is separated from an adjacent charge storage structure by anassociated multi-component dielectric structure, and wherein eachcontrol gate and associated multi-component dielectric structure has avertical dimension which is greater than the vertical dimension of theadjacent charge storage structure.
 2. The apparatus of claim 1, whereinthe vertical dimension of each control gate and associated dielectricstructure is greater than the vertical dimension of the barrier tier inwhich it is formed.
 3. The apparatus of claim 2, wherein the controlgates comprise at least one of a polysilicon and a metal.
 4. Theapparatus of claim 3, wherein the control gates comprise a metal linermaterial substantially surrounding a control gate material.
 5. Theapparatus of claim 4, wherein the metal liner material comprisestitanium nitride (TiN), tungsten nitride, or tantalum nitride.
 6. Theapparatus of claim 1, wherein the control gates comprise tungsten orpolysilicon.